Nowadays, many semiconductor memory devices are designed for working with low power supply voltages (for example, down to 1.85 V). Considering in particular a non-volatile semiconductor memory device (such as an E2PROM of the flash type), the use of a relatively low power supply voltage permits exploiting technologies based on very thin gate oxide layers, e.g. lower than 50 Å. Accordingly, it is possible to implement semiconductor memory devices that are more compact and exhibit lower power consumption.
However, in a number of applications the memory devices (albeit suitable to work at very low power supply voltages) are required to operate at higher power supply voltages (for example, 3 V or more); for example, this can happen when a memory device of a new generation has to be exploited in a system, e.g. a printed circuit board, of a previous generation (working at a higher power supply voltage).
In order to avoid the necessity to fully redesign all the existing electronic systems in which the memory devices can be used (so as to reduce their power supply voltage), countermeasures are taken by the memory device manufacturers so as to make their products directly exploitable in electronic systems working at a higher power supply voltage (so as to avoid damaging the tiny structures of the memory devices).
A typical solution is that of using dc-dc voltage-down converters for lowering the external power supply voltage to a suitable value. Preferably, the voltage-down converters are embedded in the same chip of semiconductor material wherein the memory device is integrated. Voltage-down converters known in the art consist of a voltage regulator coupled to an internal power supply line, which distributes the down-converted voltage through the chip (so as to provide it to different circuits of the memory device).
An implementation of these known voltage-down converters is based on a driver (for example, implemented with a MOS transistor), which is feedback controlled in a closed-loop configuration. This structure allows maintaining the down-converted voltage to the desired value with high accuracy (thanks to a continuous comparison between the down-converted voltage and a reference voltage).
A problem of such a solution is its stability, which can be impaired by the capacitive loads coupled to the internal power supply line; indeed, these loads can change dynamically according to the operations performed on the memory device (as a result of the enabling/disabling of different circuits thereof).
Another solution known in the art decouples the feedback circuit branch of the voltage regulator from the internal power supply line; this result is achieved by adding a distinct output stage including an additional driver (controlled by the same signal used to control the driver in the feed-back circuit branch). In this case, the operation of the feedback circuit branch is not affected by the loads coupled to the internal power supply line.
However, this open-loop solution does not permit maintaining the down-converted voltage to the desired value when the loads change dynamically (during operation of the memory device).
In any case, any transient phenomena caused by a change of the loads can have relatively long duration (at least of some tens of nanoseconds (ns)). This constraint can be incompatible with the operation of modern memory devices (which typically require current pulses with a length in the order of 50 ns).
An additional problem arises when a ripple of the down-converted voltage must be maintained within a very low range. For example, a typical situation is when this voltage is used to supply a core circuitry of the memory device (which requires a very high accuracy of its power supply voltage).